The present invention relates to the control of magnetic disk storage systems for digital computers, particularly to a sampled amplitude read channel that employs asynchronous sampling of an analog read signal, adaptive discrete time equalization, and interpolated timing recovery.
In magnetic storage systems for computers, digital data serves to modulate the current in a read/write head coil in order to write a sequence of corresponding magnetic flux transitions onto the surface of a magnetic medium in concentric, radially spaced tracks at a predetermined baud rate. When reading this recorded data, the read/write head again passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog read signal that alternate in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is xe2x80x9csegmentedxe2x80x9d into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a xe2x80x9c1xe2x80x9d bit, whereas the absence of a peak is detected as a xe2x80x9c0xe2x80x9d bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive xe2x80x9c0xe2x80x9d bits.
As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme that ensures a minimum number of xe2x80x9c0xe2x80x9d bits occur between xe2x80x9c1xe2x80x9d bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of xe2x80x9c0xe2x80x9d bits between xe2x80x9c1xe2x80x9d bits, and to k the maximum number of consecutive xe2x80x9c0xe2x80x9d bits. A typical (1,7) RLL 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier adjusts the read signal""s amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate aliasing noise. After sampling, a digital equalizer filter equalizes the sample values according to a desired partial response, and a discrete time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, xe2x80x9cPartial Response Signalingxe2x80x9d, IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, xe2x80x9cDigital Communicationxe2x80x9d, Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., xe2x80x9cThe Viterbi Algorithmxe2x80x9d, Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, xe2x80x9cA PRML System for Digital Magnetic Recordingxe2x80x9d, IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, xe2x80x9cViterbi Detection of Class IV Partial Response on a Magnetic Recording Channelxe2x80x9d, IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, xe2x80x9cImplementation of PRML in a Rigid Disk Drivexe2x80x9d, IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991; and Carley et al, xe2x80x9cAdaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detectionxe2x80x9d, Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, xe2x80x9cConstrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedbackxe2x80x9d, IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, xe2x80x9cTiming Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channelxe2x80x9d, Globecom""90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, xe2x80x9cPerformance of Digital Magnetic Recording with Equalization and Offtrack Interferencexe2x80x9d, IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, xe2x80x9cAdaptive Equalization in Magnetic-Disk Storage Channelsxe2x80x9d, IEEE Communication Magazine, February 1990; and Roger Wood, xe2x80x9cEnhanced Decision Feedback Equalizationxe2x80x9d, Intermag""90.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In conventional sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked-loop (PLL) normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error based on the difference between the estimated samples and the read signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate. Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
As mentioned above, sampled amplitude read channels also commonly employ a discrete time equalizer filter to equalize the sample values into a desired partial response (PR4, EPR4, EEPR4, etc.) before sequence detection. To this end, adaptive algorithms have been applied to compensate in real time for parameter variations in the recording system and across the disk radius. For example, U.S. Pat. No. 5,381,359 entitled xe2x80x9cAdaptation and Training of Digital Finite Impulse Response Filter Within PRML Sampling Data Detection Channelxe2x80x9d, discloses an adaptive equalizer filter that operates according to a well known least mean square (LMS) algorithm,
wk+1=wkxe2x88x92xcexcxc2x7ekxc2x7xk,
where wk represents a vector of filter coefficients; xcexc is a programmable gain; ek represents a sample error between the filter""s actual output and a desired output; and xk represents a vector of sample values from the filter input. In other words, the LMS adaptive equalizer filter is a closed loop feedback system that attempts to minimize the mean squared error between an actual output of the filter and a desired output by continuously adjusting the filter""s coefficients to achieve an optimum frequency response.
A problem associated with adaptive equalizer filters in sampled amplitude read channels is that the timing recovery and gain control loops can interfere with the adaptive feedback loop, thereby preventing the adaptive equalizer filter from converging to an optimal state. This non-convergence is manifested by the filter""s phase and gain response drifting as it competes with the timing and gain control loops. An article by J. D. Coker et al. entitled xe2x80x9cImplementation of PRML in a Rigid Disk Drivexe2x80x9d, published in IEEE Transactions on Magnetics, vol. 27, No. 6, November 1991, suggests a three tap transversal filter comprising a fixed center tap and symmetric side taps in order to constrain the phase response of the equalizer filter except in terms of a fixed group delay. Constraining the phase response of the adaptive equalizer in this manner, however, is a very sub-optimal method for attenuating interference from the timing recovery and gain control loops. Furthermore, it significantly reduces control over the adaptive filter""s phase response, thereby placing the burden of phase compensation on the analog equalizer.
Yet another problem associated with conventional adaptive equalizer filters is an inherent limitation on its order (i.e., the number of coefficients): because the adaptive equalizer is inside the timing recovery feedback loop, its order must be limited to minimize the associated transport delay. Compensating for the deficiencies of the discrete time equalizer requires filtering the analog read signal with a higher order analog equalizer prior to the timing recovery loop, which is undesirable.
There is, therefore, a need for an adaptive, discrete time equalizer filter in a sampled amplitude read channel having an improved method for constraining the phase and gain response in order to minimize interference from the timing recovery and gain control loops. A further aspect of the present invention is to remove the adaptive equalizer, and its associated latency, from the timing recovery loop, thereby allowing a higher order discrete time filter and a simplified analog filter.
A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.